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CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
.EATURES:
* * * *
IDT723622 IDT723632 IDT723642
*
* * * * * * * *
Memory storage capacity: IDT723622 - 256 x 36 x 2 IDT723632 - 512 x 36 x 2 IDT723642 - 1,024 x 36 x 2 Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Two independent clocked FIFOs buffering data in opposite directions Mailbox bypass register for each FIFO Programmable Almost-Full and Almost-Empty flags Microprocessor Interface Control Logic IRA, ORA, AEA, and AFA flags synchronized by CLKA IRB, ORB, AEB, and AFB flags synchronized by CLKB Supports clock frequencies up to 83MHz Fast access times of 8ns
Available in 132-pin Plastic Quad Flatpack (PQFP) or spacesaving 120-pin Thin Quad Flatpack (TQFP) Low-power 0.8-Micron Advanced CMOS technology Industrial temperature range (-40C to +85C) is available
DESCRIPTION:
The IDT723622/723632/723642 are a monolithic, high-speed, low-power, CMOS Bidirectional SyncFIFO (clocked) memory which supports clock frequencies up to 83MHz and have read access times as fast as 8ns. Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. These devices are a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or
.UNCTIONAL BLOCK DIAGRAM
MBF1 CLKA CSA W/RA ENA MBA Mail 1 Register Input Register RAM ARRAY 256 x 36 512 x 36 1,024 x 36 Output Register Port-A Control Logic
RST1
FIFO1, Mail1 Reset Logic
36
36
Write Pointer
Read Pointer ORB AEB
IRA AFA
FIFO 1
Status Flag Logic
FS0 FS1 A0 - A35 ORA AEA
Programmable Flag Offset Registers
10 FIFO 2
B0 - B35
Status Flag Logic Write Pointer
36
IRB AFB
36
Read Pointer
RAM ARRAY 256 x 36 512 x 36 1,024 x 36 Mail 2 Register
Output Register
FIFO2, Mail2 Reset Logic Input Register
RST2
Port-B Control Logic
CLKB CSB W/RB ENB MBB
3022 drw 01
MBF2
IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
DECEMBER 2001
DSC-3022/3
1
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED)
coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Each FIFO has a programmable Almost-Empty flag (AEA and AEB) and a progammable Almost-Full flag (AFA and AFB). AEA and AEB indicate when a selected number of words remain in the FIFO memory. AFA and AFB indicate when the FIFO contains more than a selected number of words. The Input Ready (IRA, IRB) and Almost-Full (AFA, AFB) flags of a FIFO are two-stage synchronized to the port clock that writes data into its array. The Output Ready (ORA, ORB) and Almost-Empty (AEA, AEB) flags of a FIFO are
two-stage synchronized to the port clock that reads data from its array. Offset values for the Almost-Full and Almost-Empty flags of both FIFOs can be programmed from Port A. Two or more devices may be used in parallel to create wider data paths. If, at any time, the FIFO is not actively performing a function, the chip will automatically power down. During the power down state, supply current consumption (ICC) is at a minimum. Initiating any operation (by activating control inputs will immediately take the device out of the power down state. The 723622/723632/723642 are characterized for operation from 0C to 70C. Industrial temperature range (-40C to +85C) is available by special order. They are fabricated using IDT's high speed, submicron CMOS technology.
PIN CON.IGURATION
NC NC VCC CLKB ENB W/RB CSB GND IRB ORB AFB AEB VCC MBF1 MBB RST2 FS1 GND FS0 RST1 MBA MBF2 AEA AFA VCC ORA IRA CSA W/RA ENA CLKA GND NC
NC B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND NC NC 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117
116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84
NC B11 B10 B9 B8 B7 VCC B6 GND B5 B4 B3 B2 B1 B0 GND A0 A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND NC NC
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
NC NC A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12 NC
3022 drw 02
PQFP (PQ132-1, order code: PQF) TOP VIEW
NOTES: 1. NC - no internal connection 2. Uses Yamaichi socket IC51-1324-828
2
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN CON.IGURATION (CONTINUED)
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
GND CLKA ENA W/RA CSA IRA ORA VCC AFA AEA MBF2 MBA RST1 FS0 GND FS1 RST2 MBB MBF1 VCC AEB AFB ORB IRB GND CSB W/RB ENB CLKB VCC
A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND
GND A11 A10 A9 A8 A7 A6 GND A5 A4 A3 VCC A2 A1 A0 GND B0 B1 B2 B3 B4 B5 GND B6 VCC B7 B8 B9 B10 B11
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
3022 drw 03
TQFP (PN120-1, order code: PF) TOP VIEW
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IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol A0-A35 AEA AEB AFA AFB B0 - B35 CLKA Name Port A Data Port A AlmostEmpty Flag Port B AlmostEmpty Flag Port A AlmostFull Flag Port B AlmostFull Flag Port B Data Port A Clock I/O I/0 O (Port A) O (Port B) O (Port A) O (Port B) I/O I 36-bit bidirectional data port for side A. Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is less than or equal to the value in the Almost-Empty A Offset register, X2. Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is less than or equal to the value in the Almost-Empty B Offset register, X1. Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations in FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1. Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty locations in FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2. 36-bit bidirectional data port for side B. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. IRA, ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH transition of CLKA. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. IRB, ORB, AFB, and AEB are synchronized to the LOWto-HIGH transition of CLKB. CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write on port A. The A0-A35 outputs are in the high-impedance state when CSA is HIGH. CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The B0-B35 outputs are in the high-impedance state when CSB is HIGH. ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The LOW-to-HIGH transition of a FlFO's Reset input latches the values of FS0 and FS1. If either FS0 or FS1 is HIGH when a Reset goes HIGH, one of three preset values is selected as the offset for the FlFOs Almost-Full and Almost-Empty flags. If both FIFOs are reset simultaneously and both FS0 and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to FIFO1 load the Almost-Empty and Almost-Full offsets for both FlFOs. IRA is synchronized to the LOW-to-HIGH transition of CLKA. When IRA is LOW, FIFO1 is full and writes to its array are disabled. IRA is set LOW when FIFO1 is reset and is set HIGH on the second LOW-to-HIGH transition of CLKA after reset. IRB is synchronized to the LOW-to-HIGH transition of CLKB. When IRB is LOW, FIFO2 is full and writes to its array are disabled. IRB is set LOW when FIFO2 is reset and is set HIGH on the second LOW-to-HIGH transition of CLKB after reset. A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects FIFO2 output register data for output. A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register or output and a LOW level selects FIFO1 output register data for output. MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port B read is selected and MBB is HIGH. MBF1 is set HIGH when FIFO1 is reset. MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOWto-HIGH transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is also set HIGH when FIFO2 is reset. Description
CLKB
Port B Clock
I
CSA CSB ENA ENB FS1, FS0
Port A Chip Select Port B Chip Select Port A Enable Port B Enable Flag Offset Selects
I I I I I
IRA
Input Ready Flag Input Ready Flag Port A Mailbox Select Port B Mailbox Select Mail1 Register Flag
O (Port A) O (Port B) I
IRB
MBA
MBB
I
MBF1
O
MBF2
Mail2 Register Flag
O
4
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS (CONTINUED)
Symbol ORA Name Output Ready Flag I/O O (Port A) Description ORA is synchronized to the LOW-to-HIGH transition of CLKA. When ORA is LOW, FIFO2 is empty and reads from its memory are disabled. Ready data is present on the output register of FIFO2 when ORA is HIGH. ORA is forced LOW when FlFO2 is reset and goes HIGH on the third LOW-to-HIGH transition of CLKA after a word is loaded to empty memory. ORB is synchronized to the LOW-to-HIGH transition of CLKB. When ORB is LOW, FlFO1 is empty and reads from its memory are disabled. Ready data is present on the output register of FIFO1 when ORB is HIGH. ORB is forced LOW when FIFO1 is reset and goes HIGH on the third LOW-toHIGH transition of CLKB after a word is loaded to empty memory. To reset FIFO1, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST1 is LOW. The LOW-to-HIGH transition of RST1 latches the status of FS0 and FS1 for AFA and AEB offset selection. FIFO1 must be reset upon power up before data is written to its RAM. To reset FIFO2, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST2 is LOW. The LOW-to-HIGH transition of RST2 latches the status of FS0 and FS1 for AFB and AEA offset selection. FIFO2 must be reset upon power up before data is written to its RAM. A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH. A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is LOW.
ORB
Output Ready Flag
O (Port B)
RST1
FIFO1 Reset
I
RST2
FIFO2 Reset
I
W/RA W/RB
Port A Write/ Read Select Port B Write/ Read Select
I I
5
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING .REE-AIR TEMPERATURE RANGE (Unless otherwise noted)(1)
Symbol VCC VI(2) VO(2) IIK IOK IOUT ICC TSTG Supply Voltage Range Input Voltage Range Output Voltage Range Input Clamp Current (VI < 0 or VI > VCC) Output Clamp Current (VO = < 0 or VO > VCC) Continuous Output Current (VO = 0 to VCC) Continuous Current Through VCC or GND Storage Temperature Range Rating Commercial -0.5 to 7 -0.5 to VCC+0.5 -0.5 to VCC+0.5 20 50 50 400 -65 to 150 Unit V V V mA mA mA mA C
NOTES: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIH VIL IOH IOL TA Parameter Supply Voltage (Commercial) High-Level Input Voltage (Commercial) Low-Level Input Voltage (Commercial) High-Level Output Current (Commercial) Low-Level Output Current (Commercial) Operating Temperature (Commercial) Min. 4.5 2 -- -- -- 0 Typ. 5.0 -- -- -- -- -- Max. 5.5 -- 0.8 -4 8 70 Unit V V V mA mA C
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING .REEAIR TEMPERATURE RANGE (Unless otherwise noted)
IDT723622 IDT723632 IDT723642 Commercial tCLK = 12, 15 ns Max. Min. Typ.(2) 2.4 -- -- -- -- -- -- -- -- -- -- -- -- -- 4 8 -- 0.5 10 10 8 1 -- --
Symbol VOH VOL ILI ILO ICC2(3) ICC3(3) CIN(4) COUT
(4)
Parameter Output Logic "1" Voltage Output Logic "0" Voltage Input Leakage Current (Any Input) Output Leakage Current Standby Current (with CLKA & CLKB running) Standby Current (no clocks running) Input Capacitance Output Capacitance VCC = 4.5V, VCC = 4.5V, VCC = 5.5V, VCC = 5.5V, VCC = 5.5V, VCC = 5.5V, VI = 0, VO = 0,
Test Conditions IOH = -4 mA IOL = 8 mA VI = VCC or 0 VO = VCC or 0 VI = VCC -0.2V or 0V VI = VCC -0.2V or 0V f = 1 MHz f = 1 MHZ
Unit V V A A mA mA pF pF
NOTES: 1. Industrial temperature range product is available by special order. 2. All typical values are at VCC = 5V, TA = 25C. 3. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS). 4. Characterized values, not currently tested.
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IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723622/723632/723642 with CLKA and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below. CALCULATING POWER DISSIPATION With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by: PT = VCC x [ICC(f) + (N x ICC x dc)] + (CL x VCC2 X fo) where: N ICC dc CL fo
= = = = =
number of outputs = 36 increase in power supply current for each input at a TTL HIGH level duty cycle of inputs at a TTL HIGH level of 3.4 V output capacitance load switching frequency of an output
300 fdata = 1/2 fS TA = 25C CL = 0pF 250 VCC = 5.5V VCC = 5.0V
mA Supply Current
200
150
VCC = 4.5V
ICC(f)
100
50
0 0 10 20 30 40 50 60 70 80
3022 drw 03a
90
fS Clock Frequency MHz
Figure 1. Typical Characteristics: Supply Current (ICC) vs Clock Frequency (fS)
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IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES O. SUPPLY VOLTAGE AND OPERATING .REE-AIR TEMPERATURE
(Commercial: VCC = 5V 10%, TA = 0C to +70C)
Symbol Parameter fS Clock Frequency, CLKA or CLKB tCLK tCLKH tCLKL tDS tENS1 tENS2 tRSTS tFSS tDH tENH tRSTH tFSH Clock Cycle Time, CLKA or CLKB Pulse Duration, CLKA or CLKB HIGH Pulse Duration, CLKA and CLKB LOW Setup Time, A0-A35 before CLKA and B0-B35 before CLKB Setup Time, CSA and W/RA before CLKA; CSB and W/RB before CLKB Setup Time, ENA and MBA, before CLKA; ENB and MBB before CLKB Setup Time, RST1 or RST2 LOW before CLKA or CLKB (2) Setup Time, FS0 and FS1 before RST1 and RST2 HIGH Hold Time, A0-A35 after CLKA and B0-B35 after CLKB Hold Time, CSA, W/RA, ENA, and MBA after CLKA; CSB, W/RB, ENB, and MBB after CLKB Hold Time, RST1 or RST2 LOW after CLKA or CLKB(2) Hold Time, FS0 and FS1 after RST1 and RST2 HIGH
Commercial IDT723622L12 IDT723622L15 IDT723632L12 IDT723632L15 IDT723642L12 IDT723642L15 Min. Max. Min. Max. -- 83 -- 66.7 12 5 5 3 4 3 5 7.5 0.5 0.5 4 2 7.5 12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15 6 6 4 4.5 4.5 5 7.5 1 1 4 2 7.5 12 -- -- -- -- -- -- -- -- -- -- -- -- -- --
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tSKEW1(3) Skew Time, between CLKA and CLKB for ORA, ORB, IRA, and IRB tSKEW2(3,4) Skew Time, between CLKA and CLKB for AEA, AEB, AFA, and AFB
NOTES: 1. Industrial temperature range product is available by special order. 2. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle. 4. Design simulated, not tested.
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IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES O. SUPPLY VOLTAGE AND OPERATING .REE-AIR TEMPERATURE, CL = 30 P.
(Commercial: VCC = 5V 10%, TA = 0C to +70C)
Symbol Parameter tA Access Time, CLKA to A0-A35 and CLKB to B0-B35 tPIR tPOR tPAE tPAF tPMF tPMR tMDV tRSF tEN tDIS Propagation Delay Time, CLKA to IRA and CLKB to IRB Propagation Delay Time, CLKA to ORA and CLKB to ORB Propagation Delay Time, CLKA to AEA and CLKB to AEB Propagation Delay Time, CLKA to AFA and CLKB to AFB Propagation Delay Time, CLKA to MBF1 LOW or MBF2 HIGH and CLKB to MBF2 LOW or MBF1 HIGH Propagation Delay Time, CLKA to B0-B35(2) and CLKB to A0-A35(3) Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 Valid Propagation Delay Time, RST1 LOW to AEB LOW, AFA HIGH, and MBF1 HIGH, and RST2 LOW to AEA LOW, AFB HIGH, and MBF2 HIGH Enable Time, CSA and W/RA LOW to A0-A35 Active and CSB LOW and W/RB HIGH to B0-B35 Active Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and CSB HIGH or W/RB LOW to B0-B35 at high-impedance
Commercial IDT723622L12 IDT723622L15 IDT723632L12 IDT723632L15 IDT723642L12 IDT723642L15 Min. Max. Min. Max. 2 8 2 10 2 1 1 1 0 2 2 1 2 1 8 8 8 8 8 8 8 10 6 6 2 1 1 1 0 2 2 1 2 1 8 8 8 8 8 10 10 15 10 8
Unit ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Industrial temperature range product is available by special order. 2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH. 3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
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IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
SIGNAL DESCRIPTION
RESET After power up, a Master Reset operation must be performed by providing a LOW pulse to RSTI and RST2 simultaneously. Afterwards, the FIFO memories of the IDT723622/723632/723642 are reset separately by taking their Reset (RST1, RST2) inputs LOW for at least four port A Clock (CLKA) and four port B Clock (CLKB) LOW-to-HIGH transitions. The Reset inputs can switch asynchronously to the clocks. A FIFO reset initializes the internal read and write pointers and forces the Input Ready flag (IRA, IRB) LOW, the Output Ready flag (ORA, ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW, and the AlmostFull flag (AFA, AFB) HIGH. Resetting a FIFO also forces the Mailbox Flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a FlFO is reset, its Input Ready flag is set HIGH after two clock cycles to begin normal operation. A LOW-to-HIGH transition on a FlFO Reset (RST1, RST2) input latches the value of the Flag Select (FS0, FS1) inputs for choosing the Almost-Full and Almost-Empty offset programming method (for details see Table 1, Flag Programming and the Almost-Empty Flag and Almost-Full Flag Offset Programming section that follows). The relevant FIFO Reset timing diagram can be found in Figure 2. ALMOST-EMPTY FLAG AND ALMOST-FULL FLAG OFFSET PROGRAMMING Four registers in these devices are used to hold the offset values for the Almost-Empty and Almost-Full flags. The port B Almost-Empty flag (AEB) Offset register is labeled X1 and the port A Almost-Empty flag (AEA) Offset register is labeled X2. The port A Almost-Full flag (AFA) Offset register is labeled Y1 and the port B Almost-Full flag (AFB) Offset register is labeled Y2. The index of each register name corresponds to its FIFO number. The offset registers can be loaded with preset values during the reset of a FIFO or they can be programmed from port A (see Table 1). -- PRESET VALUES To load the FIFO's Almost-Empty flag and Almost-Full flag Offset registers with one of the three preset values listed in Table 1, at least one of the flag select inputs must be HIGH during the LOW-to-HIGH transition of its Reset input. For example, to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be HIGH when FlFO1 Reset (RST1) returns HIGH. Flag offset registers associated with FIFO2 are loaded with one of the preset values in the same way with FIFO2 Reset (RST2) toggled simultaneously with FIFO1 Reset (RST1). For preset value loading timing diagram, see Figure 2.
-- PARALLEL LOAD FROM PORT A To program the X1, X2, Y1, and Y2 registers from port A, both FlFOs should be reset simultaneously with FS0 and FS1 LOW during the LOW-to-HIGH transition of the Reset inputs. After this reset is complete, the first four writes to FIFO1 do not store data in the FIFO memory but load the offset registers in the order Y1, X1, Y2, X2. The port A data inputs used by the offset registers are (A7-A0), (A8-A0), or (A9-A0) for the IDT723622, IDT723632, or IDT723642, respectively. The highest numbered input is used as the most significant bit of the binary number in each case. Valid programming values for the registers ranges from 1 to 252 for the IDT723622; 1 to 508 for the IDT723632; and 1 to 1,020 for the IDT723642. After all the offset registers are programmed from port A, the port B Input Ready flag (IRB) is set HIGH, and both FIFOs begin normal operation. See Figure 3 for relevant offset register parallel programming timing diagram. FIFO WRITE/READ OPERATION The state of the port A data (A0-A35) outputs is controlled by port A Chip Select (CSA) and port A Write/Read select (W/RA). The A0-A35 outputs are in the high-impedance state when either CSA or W/RA is HIGH. The A0-A35 outputs are active when both CSA and W/RA are LOW. Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH , MBA is LOW, and IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA is HIGH, MBA is LOW, and ORA is HIGH (see Table 2). FIFO reads and writes on port A are independent of any concurrent port B operation. Write and Read cycle timing diagrams for port A can be found in Figure 4 and 7. The port B control signals are identical to those of port A with the exception that the port B Write/Read select (W/RB) is the inverse of the port A Write/Read select (W/RA). The state of the port B data (B0-B35) outputs is controlled by the port B Chip Select (CSB) and port B Write/Read select (W/RB). The B0-B35 outputs are in the high-impedance state when either CSB is HIGH or W/RB is LOW. The B0-B35 outputs are active when CSB is LOW and W/RB is HIGH. Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is LOW, and IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs by a LOWto-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is LOW, and ORB is HIGH (see Table 3) . FIFO reads and writes on port B are independent of any concurrent port A operation. Write and Read cycle timing diagrams for port B can be found in Figure 5 and 6.
TABLE 1 .LAG PROGRAMMING
FS1 H H H H L L L FS0 H H L L H H L RST1
RST2 X
X1 AND Y1 REGlSTERS(1) 64 X 16 X 8 X Programmed from port A
X2 AND Y2 REGlSTERS(2) X 64 X 16 X 8 Programmed from port A
X
X
X
X

X
NOTES: 1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA. 2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
10
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
The setup and hold time constraints to the port Clocks for the port Chip Selects and Write/Read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is LOW during a clock cycle, the port's Chip Select and Write/Read select may change states during the setup and hold time window of the cycle. When a FIFO Output Ready flag is LOW, the next word written is automatically sent to the FIFO output register automatically by the LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH. When the Output Ready flag is HIGH, subsequent data is clocked to the output registers only when a FIFO read is selected using the port's Chip Select, Write/Read select, Enable, and Mailbox select. SYNCHRONIZED FIFO FLAGS Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve flag-signal reliability by reducing the probability of metastable events when CLKA and CLKB operate asynchronously to one another. ORA, AEA, IRA, and AFA are synchronized to CLKA. ORB, AEB, IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2. OUTPUT READY FLAGS (ORA, ORB) The Output Ready flag of a FIFO is synchronized to the port clock that reads data from its array. When the Output Ready flag is HIGH, new data is present in the FIFO output register. When the Output Ready flag is LOW, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored.
A FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine that controls an Output Ready flag monitors a write pointer and read pointer comparator that indicates when the FIFO memory status is empty, empty+1, or empty+2. From the time a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of the Output Ready flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in memory is the next data to be sent to the FlFO output register and three cycles of the port Clock that reads data from the FIFO have not elapsed since the time the word was written. The Output Ready flag of the FIFO remains LOW until the third LOW-to-HIGH transition of the synchronizing clock occurs, simultaneously forcing the Output Ready flag HIGH and shifting the word to the FIFO output register. A LOW-to-HIGH transition on an Output Ready flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 8 and 9 for ORA and ORB timing diagrams). INPUT READY FLAGS (IRA, IRB) The Input Ready flag of a FlFO is synchronized to the port clock that writes data to its array. When the Input Ready flag is HIGH, a memory location is free in the FIFO to receive new data. No memory locations are free when the Input Ready flag is LOW and attempted writes to the FIFO are ignored. Each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls an Input Ready flag monitors a write pointer and read pointer comparator that indicates when the FlFO memory status is full, full-1, or
TABLE 2 PORT A ENABLE .UNCTION TABLE
CSA H L L L L L L L W/RA X H H H L L L L ENA X L H H L H L H MBA X X L H L L H H CLKA X X

Data A (A0-A35) I/O High-Impedance Input Input Input Output Output Output Output
PORT FUNCTION None None FIFO1 write Mail1 write None FIFO2 read None Mail2 read (set MBF2 HIGH)
X
X
TABLE 3 PORT B ENABLE .UNCTION TABLE
CSB H L L L L L L L W/RB X L L L H H H H ENB X L H H L H L H MBB X X L H L L H H CLKB X X

Data B (B0-B35) I/O High-Impedance Input Input Input Output Output Output Output
11
PORT FUNCTION None None FIFO2 write Mail2 write None FIFO1 read None Mail1 read (set MBF1 HIGH)
X
X
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
full-2. From the time a word is read from a FIFO, its previous memory location is ready to be written in a minimum of two cycles of the Input Ready flag synchronizing clock. Therefore, an Input Ready flag is LOW if less than two cycles of the Input Ready flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the Input Ready flag synchronizing Clock after the read sets the Input Ready flag HIGH. A LOW-to-HIGH transition on an Input Ready flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 10 and 11 for timing diagrams). ALMOST-EMPTY FLAGS (AEA, AEB) The Almost-Empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an Almost-Empty flag monitors a write pointer and read pointer comparator that indicates when the FIFO memory status is almost-empty, almost-empty+1, or almost-empty+2. The
almost-empty state is defined by the contents of register X1 for AEB and register X2 for AEA. These registers are loaded with preset values during a FIFO reset or programmed from port A (see Almost-Empty flag and Almost-Full flag offset programming section). An Almost-Empty flag is LOW when its FIFO contains X or less words and is HIGH when its FIFO contains (X+1) or more words. A data word present in the FIFO output register has been read from memory. Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing clock are required after a FIFO write for its Almost-Empty flag to reflect the new level of fill. Therefore, the Almost-Full flag of a FIFO containing (X+1) or more words remains LOW if two cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (X+1) level. An Almost-Empty flag is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of an Almost-Empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle. (See Figures 12 and 13).
TABLE 4 .I.O1 .LAG OPERATION
IDT723622(3) 0 1 to X1 (X1+1) to [256-(Y1+1)] (256-Y1) to 255 256 Number of Words in FIFO(1,2) IDT723632(3) 0 1 to X1 (X1+1) to [512-(Y1+1)] (512-Y1) to 511 512 IDT723642(3) 0 1 to X1 (X1+1) to [1,024-(Y1+1)] (1,024-Y1) to 1,023 1,024 Synchronized to CLKB ORB AEB L L H H H H L H H H Synchronized to CLKA AFA IRA H H H H L L H H H L
NOTES: 1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free. 2. Data in the output register does not count as a "word in FIFO memory". Since the first word written to an empty FIFO goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count. 3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of FIFO1 or programmed from port A.
TABLE 5 .I.O2 .LAG OPERATION
IDT723622(3) 0 1 to X2 (X2+1) to [256-(Y2+1)] (256-Y2) to 255 256 Number of Words in FIFO(1,2) IDT723632(3) 0 1 to X2 (X2+1) to [512-(Y2+1)] (512-Y2) to 511 512 IDT723642(3) 0 1 to X2 (X2+1) to [1,024-(Y2+1)] (1,024-Y2) to 1,023 1,024 Synchronized to CLKA ORA AEA L H H H H L L H H H Synchronized to CLKB AFB IRB H H H L L H H H H L
NOTES: 1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free. 2. Data in the output register does not count as a "word in FIFO memory". Since the first word written to an empty FIFO goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count. 3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset of FIFO2 or programmed from port A.
12
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ALMOST-FULL FLAGS (AFA, AFB) The Almost-Full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine that controls an Almost-Full flag monitors a write pointer and read pointer comparator that indicates when the FIFO memory status is almost-full, almost-full-1, or almost-full-2. The almost-full state is defined by the contents of register Y1 for AFA and register Y2 for AFB. These registers are loaded with preset values during a FlFO reset or programmed from port A (see Almost-Empty flag and Almost-Full flag offset programming section). An Almost-Full flag is LOW when the number of words in its FIFO is greater than or equal to (256-Y), (512-Y), or (1,024-Y) for the IDT723622, IDT723632, or IDT723642 respectively. An Almost-Full flag is HIGH when the number of words in its FIFO is less than or equal to [256-(Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the IDT723622, IDT723632, or IDT723642 respectively. Note that a data word present in the FIFO output register has been read from memory. Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock are required after a FIFO read for its Almost-Full flag to reflect the new level of fill. Therefore, the Almost-Full flag of a FIFO containing [256/512/1,024-(Y+1)] or less words remains LOW if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in memory to [256/ 512/1,024-(Y+1)]. An Almost-Full flag is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after the FIFO read that reduces the number of words in memory to [256/512/1,024-(Y+1)]. A LOW-to-HIGH transition of an Almost-Full flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the read that reduces the number of words
in memory to [256/512/1,024-(Y+1)]. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle (see Figures 14 and 15). MAILBOX REGISTERS Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B without putting it in queue. The Mailbox select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. A LOW-to-HIGH transition on CLKA writes A0-A35 data to the mail1 register when a port A Write is selected by CSA, W/RA, and ENA and with MBA HIGH. A LOW-to-HIGH transition on CLKB writes B0-B35 data to the mail2 register when a port B Write is selected by CSB, W/ RB, and ENB and with MBB HIGH. Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while the mail flag is LOW. When data outputs of a port are active, the data on the bus comes from the FIFO output register when the port Mailbox select input is LOW and from the mail register when the port-mailbox select input is HIGH. The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when a port B Read is selected by CSB, W/RB, and ENB and with MBB HIGH. The Mail2 Register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when a port A read is selected by CSA, W/RA, and ENA and with MBA HIGH. The data in a mail register remains intact after it is read and changes only when new data is written to the register. For mail register and Mail Register flag timing diagrams, see Figure 16 and 17.
13
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
CLKA tRSTH CLKB tRSTS RST1 FS1,FS0 tPIR IRA tPOR ORB tRSF AEB tRSF AFA tRSF MBF1
NOTE: 1. FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.
COMMERCIAL TEMPERATURE RANGE
tFSS
tFSH
0,1 tPIR
3022 drw 04
Figure 2. FIFO1 Reset and Loading X1 and Y1 with a Preset Value of Eight(1)
CLKA RST1, RST2 FS1,FS0
4
1 tFSS
2
tFSH 0,0 tPIR
IRA ENA tDS A0 - A35
AFA Offset (Y1)
tENS2
tENH
tSKEW1
(1)
tDH
AEB Offset (X1) AFB Offset (Y2) AEA Offset (X2) First Word to FIFO1
CLKB
1
2 tPIR
IRB
3022 drw 05
NOTES: 1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising edge of CLKB is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown. 2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
Figure 3. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
14
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK tCLKH CLKA IRA HIGH CSA W/RA tENS2 MBA tENS2 ENA tDS A0 - A35
NOTE: 1. Written to FIFO1.
tCLKL
tENS1 tENS1
tENH tENH
tENH
tENH tDH W1(1)
tENS2
tENH
tENS2
tENH
W2(1)
No Operation
3022 drw 06
Figure 4. Port A Write Cycle Timing for FIFO1
tCLK tCLKH CLKB IRB CSB tENS1 W/RB tENS2 MBB tENS2 ENB B0 - B35
NOTE: 1. Written to FIFO2.
tCLKL
HIGH
tENS1
tENH
tENH tENH tENH tDH W2(1) No Operation
3022 drw 07
tENS2
tENH
tENS2
tENH
tDS W1(1)
Figure 5. Port B Write Cycle Timing for FIFO2
15
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK tCLKH CLKB tCLKL
ORB HIGH CSB W/RB
tENS2
MBB tENH ENB tMDV B0 - B35
NOTE: 1. Read From FIFO1.
tENS2
tENH
tENS2 No Operation
tENH
tEN
tA W1(1) W2(1)
tA W3 (1)
tDIS
3022 drw 08
Figure 6. Port B Read Cycle Timing for FIFO1
tCLK tCLKH CLKA ORA CSA tCLKL
W/RA tENS2 MBA tENH ENA tDMV tEN A0 - A35
NOTE: 1. Read From FIFO2.
tENS2
tENH tENS2 No Operation
tENH
tA W1(1) W2(1)
tA W3(1)
tDIS
3022 drw 09
Figure 7. Port A Read Cycle Timing for FIFO2
16
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
tCLK tCLKH CLKA CSA LOW tCLKL
COMMERCIAL TEMPERATURE RANGE
WRA MBA
HIGH
tENS2
tENH
tENS2 ENA
tENH
IRA A0 - A35
HIGH
tDS W1
tDH
tSKEW1 CLKB ORB CSB FIFO1 Empty LOW
(1)
tCLKH 1
tCLK tCLKL 2 3 tPOR tPOR
W/RB MBB
HIGH LOW tENS2 tENH
ENB tA B0 - B35
Old Data in FIFO1 Output Register W1
4660 drw 10
NOTE: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB cycle later than shown.
Figure 8. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty
17
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLKH CLKB CSB LOW W/RB LOW tENS2 MBB tENS2 ENB IRB HIGH B0 - B35 tDS W1
(1)
tCLK
tCLKL
tENH tENH
tDH tCLK tCLKL 2 3 tPOR tPOR
tSKEW1 CLKA ORA FIFO2 Empty CSA LOW W/RA LOW MBA LOW
tCLKH 1
tENS2 ENA tA A0-A35 Old Data in FIFO2 Output Register
tENH
W1
3022 drw 11
NOTE: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA cycle later than shown.
Figure 9. ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty
18
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK tCLKH CLKB CSB W/RB MBB ENB LOW HIGH LOW tENS2 tENH tCLKL
ORB B0 -B35
HIGH
tA
Next Word From FIFO1
(1)
Previous Word in FIFO1 Output Register
tSKEW1 CLKA IRA CSA W/RA MBA FIFO1 Full LOW HIGH
tCLKH 1
tCLK
tCLKL 2 tPIR tPIR
tENS2 tENS2
tENH tENH tDH
Write To FIFO1
3022 drw 12
ENA tDS A0-A35
NOTE: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
Figure 10. IRA Flag Timing and First Available Write when FIFO1 is Full
19
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
tCLK
COMMERCIAL TEMPERATURE RANGE
tCLKH CLKA CSA W/RA MBA ENA ORA A0 -A35 HIGH LOW LOW LOW
tCLKL
tENS2
tENH
tA
Next Word From FIFO2
(1)
Previous Word in FIFO2 Output Register
tSKEW1 CLKB IRB CSB W/RB MBB FIFO2 FULL LOW LOW
tCLKH 1
tCLK
tCLKL 2 tPIR tPIR
tENS2 tENS2 ENB tDS B0 - B35
Wriite To FIFO2
tENH tENH tDH
3022 drw 13
NOTE: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.
Figure 11. IRB Flag Timing and First Available Write when FIFO2 is Full
CLKA tENS2 ENA tSKEW2 CLKB AEB ENB
3022 drw 14 (1)
tENH
1
X1 Words in FIFO1
2 tPAE
(X1+1) Words in FIFO1
tPAE tENS2 tENH
NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown. 2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
Figure 12. Timing for AEB when FIFO1 is Almost-Empty
20
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKB tEN2S ENB tSKEW2 CLKA AEA ENA
3022 drw 15 (1)
tENH
1
X2 Words in FIFO2
2 tPAE
(X2+1) Words in FIFO2
tPAE tENS2 tENH
NOTES: 1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown. 2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
Figure 13. Timing for AEA when FIFO2 is Almost-Empty
tSKEW2 CLKA tENS2 ENA tPAF AFA CLKB tENS2 ENB tENH
[D-(Y1+1)] Words in FIFO1
(1)
1 tENH
2
tPAF
(D-Y1) Words in FIFO1
3022 drw 16
NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown. 2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO. 3. D = Maximum FIFO Depth = 256 for the IDT723622, 512 for the IDT723632, 1,024 for the IDT723642.
Figure 14. Timing for AFA when FIFO1 is Almost-Full
21
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tSKEW2 CLKB tENS2 ENB tPAF AFB CLKA tENS2 ENA tENH [D-(Y2+1)] Words in FIFO2 tENH
(1)
1
2
tPAF (D-Y2) Words in FIFO2
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NOTES: 1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKB cycle later than shown. 2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO. 3. D = Maximum FIFO Depth = 256 for the IDT723622, 512 for the IDT723632, 1,024 for the IDT723642.
Figure 15. Timing for AFB when FIFO2 is Almost-Full
CLKA tENS1 CSA tENS1 W/RA tENS2 MBA tENS2 ENA A0 - A35 CLKB tPMF MBF1 CSB W/RB MBB ENB tEN B0 - B35 tMDV FIFO1 Output Register tPMR tDIS W1 (Remains valid in Mail1 Register after read)
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tENH tENH tENH tENH
tDS W1
tDH
tPMF
tENS2
tENH
Figure 16. Timing for Mail1 Register and MBF1 Flag
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IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
CLKB tENS1 CSB tENS1 W/RB tENS2 MBB tENS2 ENB tDS W1 tDH tENH tENH tENH tENH
COMMERCIAL TEMPERATURE RANGE
B0-B35
CLKA tPMF MBF2 CSA W/RA tPMF
MBA tENS2 ENA tEN A0-A35 FIFO2 Output Register tPMR tMDV
tENH
tDIS W1 (Remains valid in Mail 2 Register after read)
3022 drw19
Figure 17. Timing for Mail2 Register and MBF2 Flag
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IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PARAMETER MEASUREMENT INFORMATION
5V 1.1 k From Output Under Test 680 30 pF
(1)
PROPAGATION DELAY LOAD CIRCUIT 3V Timing Input tS Data, Enable Input 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable tPLZ Low-Level Output tPZH High-Level tPHZ Output VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
NOTE: 1. Includes probe and jig capacitance.
1.5 V GND th 3V 1.5 V GND
High-Level Input
3V 1.5 V tW 3V 1.5 V GND
Low-Level Input
1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS
1.5 V GND
3V 1.5 V 1.5 V tPZL 1.5 V VOL VOH 1.5 V OV In-Phase Output GND 3 V Input 3V 1.5 V tPD 1.5 V 1.5 V GND tPD VOH 1.5 V VOL
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VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
Figure 18. Load Circuit and Voltage Waveforms
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ORDERING IN.ORMATION
IDT XXXXXX Device Type X Power XX Speed X Package X Process/ Temperature Range BLANK PF PQF 12 15 L 723622 723632 723642
NOTE: 1. Industrial temperature range is available by special order.
Commercial (0C to +70C) Thin Quad Flat Pack (TQFP, PN120-1) Plastic Quad Flat Pack (PQFP, PQ132-1) Clock Cycle Time (tCLK) Speed in Nanoseconds
Commercial Only Low Power
256 x 36 x 2 SyncBiFIFO 512 x 36 x 2 SyncBiFIFO 1,024 x 36 x 2 SyncBiFIFO
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DATASHEET DOCUMENT HISTORY
10/04/2000 03/21/2001 08/01/2001 12/18/2001 pgs. 1 through 25, except pages 3 and 5. pgs. 6 and 7. pgs. 1, 6, 8, 9 and 25. pg. 23. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
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for TECH SUPPORT: 408-330-1753 FIFOhelp@idt.com

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